The electronics industry has experienced an ever increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. However, continued scaling of FinFET devices has also led to issues such as increased difficulty for deployment of strained layers on narrow fin structures, as well as a reduced contact landing margin and increased contact resistance. In addition, for FinFET devices having a one-step fin profile, it may be challenging to provide well control due to the disparate requirements of a tapered fin profile (e.g., straight near the top of the fin and rounded near the bottom of the fin). While two-step fin profiles may address some of the above issues, conventional patterning of two-step fin profiles includes patterning of critical features using photolithographic techniques. As is well-known, photolithography processes are limited in their alignment precision, and repeatability, of the equipment used (e.g., a photolithography stepper). Thus, FinFET critical dimensions (CDs) may be directly impacted by misalignment of critical features during photolithography. Moreover, alignment errors can lead to degraded device performance and/or device failure. Thus, existing techniques have not proved entirely satisfactory in all respects.